Sigma delta converter insensitive to asymmetrical switching times
US5196853A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1991 |
| Grant date | Mar 23, 1993 |
| Priority date | — |
| Expiry date | Nov 25, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Sigma-delta converter for converting an analog input signal into a sigma-delta code. The converter includes a threshold device (222) for generating an output and feedback signal, a filter receiving said analog input signal and said feedback signal from at least one feedback loop. The sigma-delta converter further includes circuits (221, 222) located in said feedback loop for performing a return-to-zero of the sigma-delta code generated by said threshold device at every period of the sigma delta clock, whereby said sigma-delta converter is insensitive to the asymmetry of the rise and fall time of the threshold device. This results in an increase of the signal-to-noise ratio and linearity of the converter, allowing the manufacture of a sigma-delta convertor with discrete components without requiring the development of an integrated circuit using switched capacitor technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.