Semiconductor memory device with dual reference elements
US5197028A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 16, 1990 |
| Grant date | Mar 23, 1993 |
| Priority date | — |
| Expiry date | Aug 16, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention involves a semiconductor memory device having a memory cell with a drain, a gate and a source. The gate of the memory cell is supplied with a first potential for reading a memory cell data. A first reference line is connected to the drain of a first reference cell to receive a first reference cell data. A second reference cell has a drain, a gate and a source. A second reference line is connected to the drain of the second reference cell for receiving a second reference cell data. A gate voltage generating circuit having an output node is connected to the gate of the first reference cell for controlling the gate potential of the first reference cell so that the potentials at the first and second reference lines have the same power source voltage dependancy. A data detecting circuit reads the memory cell data in accordance with the comparison result between the potentials.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.