High speed digital clock synchronizer
US5197086A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1990 |
| Grant date | Mar 23, 1993 |
| Priority date | — |
| Expiry date | Dec 28, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D3/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A synchronization system for locking a data input signal to a local clock uses the data input signal to provide the timing for capturing phase waveforms generated by a delay element string and a local oscillator. A transition detector generates bit patterns which correspond to a captured phase waveform which is in synch with the data input signal. The bit pattern of the captured in synch waveform is stored in a storage device under control of window detection and control logic also timed by the data input signal. The control logic stores a new bit pattern of a new phase waveform when the window detection logic determines that the new bit pattern is outside a 2-bit window and then selects the new phase waveform correponding to the new bit pattern for clocking the data input signal if the new bit pattern hasn't changed after N consecutive cycles of the data input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.