Barrier layer device processing
US5198881A · kind A · utility
2Cited by
15References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 1991 |
| Grant date | Mar 30, 1993 |
| Priority date | — |
| Expiry date | Aug 7, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/153
Abstract
A surface electron barrier region is formed on a semiconductor membrane device by a single step laser process which produces a sharp doping profile in a surface region above the light penetration depth. Enhanced quantum efficiency is observed, and by selectively forming barrier layers of differing depth, a CCD device architecture for two-color sensitivity is achieved. The barrier layer results in enhanced membrane-type and radiation hardened bipolar and CMOS devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.