High frequency master/slave flip-flops
US5200650A · kind A · utility
8Cited by
5References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1990 |
| Grant date | Apr 6, 1993 |
| Priority date | — |
| Expiry date | Nov 21, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A D-type, master/slave, flip-flop is described for use as a divide-by-2 frequency divider in which a frequency to be divided is input as a clock signal and the Q output is connected to the D input, and in which the master section and the slave section consist only of tracking means, latching being effected by using potentials established on tracking transistors of each section during the previous clock pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.