Tristate output gate structure particularly for CMOS integrated circuits
US5200653A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 1991 |
| Grant date | Apr 6, 1993 |
| Priority date | — |
| Expiry date | Jun 21, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09429
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The tristate output gate structure particularly for CMOS integrated circuits, comprises an enable terminal receiving an enable signal and an input terminal receiving an input signal, which connects, through signal switching means, an output terminal to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor through signal inverting means and to the gate terminal of a second N-channel transistor. The output terminal is electrically connected to the drain terminals of the first and second transistors. The first and second transistors electrically insulate the output terminal from the input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.