Synchronizing system
US5200976A · kind A · utility
3Cited by
3References
10Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 16, 1990 |
| Grant date | Apr 6, 1993 |
| Priority date | — |
| Expiry date | Nov 16, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a synchronizing circuit, such as a DPLL (Digital Phase-Locked Loop), adapted to be synchronized in accordance with clock signals of an external clock, a programmable timer in the circuit is forcedly reset in synchronism with the edge of an external clock signal pulse at the time of the clock signal's initial state in accordance with a clock detection circuit. Subsequently, baud timing of the external clock signals is detected by making use of internal clock signals produced by the circuit. Synchronism is thus established and maintained between the circuit and the external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.