In-line piece-wise linear desynchronizer
US5200982A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 2, 1991 |
| Grant date | Apr 6, 1993 |
| Priority date | — |
| Expiry date | Oct 2, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/076
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An in-line piece-wise linear desynchronizer eliminates the need for very low bandwidth analog, phase lock loops to smooth phase jumps caused by pointer changes such as those associated with a DS-1 signal mapped into a SONET VT 1.5 payload. The desynchronizer comprises a digital elastic store position detection circuit, a digital frame induced jitter filter, a digital leak rate filter, and a digital frequency synthesizer (VCO). The magnitude of the jitter can be reduced to any level by adjusting the digital VCO resolution and digital leak rate filter time constant. The desynchronizer produces a digitally synthesized output clock which can then be coupled to an analog/digital phase lock loop for smoothing high frequency jitter in the synthesized output clock, thereby providing an in-line interface function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.