Multiple address-space data processor with addressable register and context switching
US5201039A · kind A · utility
459Cited by
9References
16Claims
0Family size
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Key dates
| Filing date | Aug 20, 1990 |
| Grant date | Apr 6, 1993 |
| Priority date | — |
| Expiry date | Aug 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/463
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two or more address spaces are provided in a data processor. One of the address spaces comprises control registers so that the control registers can be accessed using instructions having an address in the second address space. High-speed context switching can be accomplished by allotting the context-saving area to the second address space. The context can be saved in various formats specified by a context format register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.