System using both a supervisor level control bit and a user level control bit to enable/disable memory reference alignment checking
US5201043A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 1992 |
| Grant date | Apr 6, 1993 |
| Priority date | — |
| Expiry date | Jun 10, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor which includes means for detecting misaligned data reference is described. The detecting means is selectable such that when it is enabled and reference is made to a misaligned data object, a fault is produced which interrupts the currently executing program. The detecting means comprises two mode bits stored within the microprocessor. The first mode bit provides control of the fault at the least privileged level of execution (i.e., the applications level) while the second mode bit provides control of the fault at the most privileged level (i.e., the operating system level). Both mode bits must be set to "1" in order for the detecting means to be enabled. The use of two separate mode bits for optionally enabling alignment checking provides optimum programming flexibility.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.