Field effect transistor formed with deep-submicron gate
US5202272A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1991 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Mar 25, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure comprising the steps of: providing a body of semiconductor material including at least one generally planar surface; forming a mesa having at least one generally vertical wall over the planar surface; forming a layer of material generally conformally over the mesa and the planar surface so as to form a vertical spacer on the vertical wall; forming a protective mask selectively on the upper portion of the vertical spacer; and using the protective mask to etch and remove the unmasked portions of the layer of material and the mesa while leaving the vertical spacer. The process is used to form an FET by forming a gate insulating layer underneath of the vertical spacer, the vertical spacer being selected to comprise a conductive gate material such as doped polysilicon. The vertical gate structure is then used as a mask to dope the source and drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.