Sampled-data control system exhibiting reduced phase loss
US5202821A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1991 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Jun 28, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B21/02
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
An automatic digital control system includes a proportional integral derivative (PID) compensator in which the digital differentiator portion, with its associated zero-order hold, is implemented according to an algorithm that reduces phase loss as a function of frequency. The digital differentiator is based only on a present error sample so that the output of the digital differentiator (with its ZOH) is made to resemble an amplitude-balanced step function (i.e., a doublet) during a given sample period T. The step transition occurs at one-half of the period (i.e., at T/2). Another embodiment further reduces phase loss by confining the output waveform of the differentiator to some fraction of the total sampling period. During the remaining portion of the sampling period the digital differentiator (again, with its associated ZOH) is forced to some desired reference level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.