Expansion system
US5202968A · kind A · utility
13Cited by
9References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 10, 1991 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Sep 10, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache LSI has an expansion pin which is set to "0" (GND) level or "1" (Vcc) level. A portion of a SET field of a cache directory is used as a field for selecting a cache LSI. Each cache LSI includes a determination circuit. The determination circuit performs a predetermined logical operation based on a level signal set at the expansion pin and a level signal of the cache selection field in the SET field, and determines whether or not an intra-chip is selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.