Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively
US5202969A · kind A · utility
53Cited by
16References
20Claims
0Family size
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Key dates
| Filing date | Apr 21, 1992 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Apr 21, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.