Store buffer apparatus in a multiprocessor system
US5202972A · kind A · utility
47Cited by
19References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 3, 1991 |
| Grant date | Apr 13, 1993 |
| Priority date | — |
| Expiry date | Jul 3, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0811
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiprocessor computer system has a common master storage and data/instruction caches for each processor. Separate buffer storage units for each processor read data from the processor in parallel with the caches, but write data to the master storage sequentially, as directed by a controller for the master storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.