Logic array having high frequency internal clocking
US5204555A · kind A · utility
56Cited by
7References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 2, 1992 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Apr 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17716
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A state machine is configured with a phase-locked loop clock signal generator which can operate at a rate faster than an externally generated reference clock signal applied to the phase-locked loop. The output of the phase-locked loop is used to trigger registers coupled to the state machine at a selected rate to enable signals at output terminals of the state machine to be updated at a rate different than the rate of the externally generated reference clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.