Method and apparatus for controlling clock skew
US5204559A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1991 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Jan 23, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for controlling clock skew has a plurality of delay elements placed in each of the clock output paths in a clock distribution circuit. The delay elements may be selectively switched into or out of each clock output path in order to adjust the delays of each clock output path so that the skew between clock outputs is minimized. The delay in each clock output path is determined by measuring the frequency of a ring oscillator created by connecting a feedback loop across the delay elements. The frequency of oscillation is measured as delay elements are switched into or out of each clock output path until the frequency reaches close to a target frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.