Combined sense amplifier and latching circuit for high speed roms
US5204560A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1991 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Oct 4, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A combined sense amplifier and latching circuit receives an input signal (VIN) at an input terminal (22). A sense amplifier includes a gated-loop type master latch (ML) having two cascaded inverters (I12, I13) with a common node (I) coupled therebetween and a control device (TG4) in the master latch loop controlled by a gating signal (55A). A reference voltage generator generates a reference voltage (VREF). The two inverters are biased between a first supply voltage (Vdd) having a magnitude greater than the reference voltage and either a second supply voltage (GND) or the reference voltage depending on the value of the gating signal. The input terminal is connected to the input of one of the inverters. A gated-loop slave latch (SL) is connected in series with the sense amplifier and includes two cascaded inverters (I14, I15) with a common node (M) coupled therebetween and a control device (P15) in the slave latch loop controlled by the gating signal. The sense amplifier and the slave latch are isolated from each other by a control device (TG5) controlled by the gating signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.