Gate control circuit for MOS transistor
US5204561A · kind A · utility
12Cited by
11References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 16, 1990 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Jul 16, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/687
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate control circuit is provided for a power MOS transistor (T) having an input capacitance (C.sub.e). The transistor gate is in series with an inductance (L). The inductance is initially precharged. First switch, element (T2, T3) transfers the energy stored in the inductance towards the input capacitance during a switching on condition of the power MOS transistor. Second switch element (T1, T4) transfers back the energy stored in the input capacitance back to the inductance during a switching off condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.