Intrinsic offset recovery circuit particularly for amplifiers
US5204638A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 1991 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Dec 17, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/3437
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Intrinsic offset recovery circuit particularly for amplifiers, which comprises an input differential amplifier constituted by a first PNP transistor, by a second PNP transistor, by a third NPN transistor, by a fourth NPN transistor and by a first constant-current source, and a unitary-gain output stage. The recovery circuit furthermore comprises, as connection between the input differential amplifier and the unitary-gain output stage, a gain stage which comprises a fifth NPN transistor which is connected to the output of the input differential amplifier and is connected to a sixth NPN transistor and to a seventh PNP transistor. The seventh transistor is connected to the sixth transistor. The seventh transistor and the sixth transistor are connected to the unitary-gain output stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.