Time base correcting apparatus with means for inhibiting memory write and read addresses to prevent address overlap
US5204787A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 1990 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Nov 26, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/956
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a time base correcting apparatus having a memory for storing a reproduced video signal reproduced by a rotary magnetic head from slant tracks on a magnetic tape which is transported at a desired tape running speed that may be different from a tape running speed used when recording the video signal on the tape, a write in-line address counter for generating a write in-line address signal and a write line address counter for generating a write line address signal supplied to the memory, a write clock signal generating circuit for generating a write in-line address increment clock signal and a write line address increment clock signal which are each synchronized with a reproduced horizontal synchronizing signal separated from the reproduced video signal, and which are supplied to the write in-line address counter and the write line address counter, a read in-line address counter for generating a read in-line address signal and a read line address counter for generating a read line address signal supplied to the memory, and a read clock signal generating circuit for generating a read in-line address increment clock signal and a read line address increment clock signal which are each…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.