Duplex processor arrangement for a switching system
US5204952A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 1991 |
| Grant date | Apr 20, 1993 |
| Priority date | — |
| Expiry date | Jul 23, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a duplex processor arrangement wherein the processors are only pseudo-synchronized to each other. Each processor is provided with its own independent clock circuit and the two clock circuits operate at the same nominal frequency. A circuit means is provided for periodically forcing a rendezvous between processors whereat a controller circuit ensures that the processors have processed the same information since the last rendezvous. Each processor comprises a match circuit including memory means connected to store address/data information related to instructions performed by the processors. Each match circuit compares the information from the processors and generates an alarm signal upon a mismatch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.