Logic circuit including variable impedance means
US5206546A · kind A · utility
39Cited by
10References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Aug 1, 1991 |
| Grant date | Apr 27, 1993 |
| Priority date | — |
| Expiry date | Aug 1, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0136
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A SPL (or Super Push-pull Logic) circuit is provided which includes: a first variable resistor circuit connected between the collector of an input transistor and a first supply voltage terminal (GND) a second variable resistor circuit connected between the emitter of the input transistor and a second supply voltage terminal (V.sub.EE) and a push-pull output circuit. The second variable resistor circuit includes an N-channel MOSFET which has its gate electrode made receptive of any of the output signals of the SPL circuit, a differentiated signal of the output signal, and an inverted signal of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.