Methods for testing integrated circuit devices
US5206585A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 1991 |
| Grant date | Apr 27, 1993 |
| Priority date | — |
| Expiry date | Dec 2, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/0408
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for testing an integrated circuit (IC) chip (10) in accordance with the invention comprises the step of forming a solder bump (14) on each of an array of bonding pads (13) on a first surface of the chip, in accordance with the known flip-chip method of IC device packaging. Each of the solder bumps (14) is inserted through an aperture (25) in a spacer member (22), the spacer member having a smaller thickness than the length of each solder bump, whereby each solder bump protrudes through an aperture. The solder bumps are then placed on a layer of anisotropic conductive material (11) which is arranged over an array of test fixture conductive pads so that the anisotropic conductive layer is sandwiched between the IC chip and the test fixture. The integrated circuit chip is then compressed against the anisotropic conductor material to establish electrical contact between the solder bumps of the integrated circuit chip and the test fixture conductor pads (17). The testing of the chip then proceeds by passing electrical current through the solder bumps, the anisotropic material, and the test fixture conductor pads in a known manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.