Charge-controlled integrating successive-approximation analog-to-digital converter
US5206650A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1991 |
| Grant date | Apr 27, 1993 |
| Priority date | — |
| Expiry date | Sep 5, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A charge-controlled integrating successive-approximation analog-to-digital converter first stores a charge proportional to an unknown voltage in a manner similar to a dual-slope integrating ADC, and thereafter a successive-approximation binary search sequence algorithm is applied to the integrator to determine digital bits representative of the unknown voltage. The result is a relatively simple and inexpensive ADC having high resolution and accuracy, and comparatively fast conversion rates, and exhibiting low power consumption, high noise rejection, and multiple-speed versatility. The preferred embodiment described is a 16-bit ADC with less than 20 millisecond conversion time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.