Patent · US Expired

Apparatus and method for fast I/O data transfer in an intelligent cell

US5206935A · kind A · utility

8Cited by
15References
11Claims
0Family size

Inventors

Key dates

Filing dateMar 26, 1991
Grant dateApr 27, 1993
Priority date
Expiry dateMar 26, 2011

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F13/32
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A specialized apparatus and method for providing fast programmed I/O for transferring information in a multi-processor environment which includes a CPU, and a memory coupled to an I/O port across an internal data bus. Multiple bytes of data are transferred in successive processing cycles to the I/O port from the memory, or from the I/O to the memory by first determining the upper limit for the number of bytes that are going to be transferred. This number and the memory start address are then stored in CPU registers. The I/O module is then checked by the CPU to see if a data byte is available from an external device. If a data byte is available, the I/O module is instructed to place the data byte on the bus for storage within the memory at the start address. The address is then incremented and the count is decremented. The above procedure is repeated until the count drops to zero, after which time the next instruction is fetched.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.