Manufacturing a semiconductor integrated circuit device having on chip logic correction
US5208178A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 31, 1991 |
| Grant date | May 4, 1993 |
| Priority date | — |
| Expiry date | Jul 31, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention relates to a logic correction for a random logic IC of a high integration density, and more particularly to an on-chip logic correction method wherein the upper surface of a chip is divided into a large number of macrocells, testing of the macrocells is made and each defective macrocell is corrected by replacement. Testing is performed after a primary wiring process that connects semiconductor elements into macrocells but before a secondary wiring process interconnecting the macrocells. After the testing, defective macrocells are replaced, and thereafter the secondary wiring process is performed. Testing is performed using testing pads in each macrocell, connected to the main circuit portion of the macrocell through shift register circuit portions. The macrocells are arranged in a lattice pattern. Wirings formed in the secondary wiring process have a larger cross-sectional area than wirings formed in the primary wiring process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.