Cycle up convergence of electrostatics in a tri-level imaging apparatus
US5208632A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1991 |
| Grant date | May 4, 1993 |
| Priority date | — |
| Expiry date | Sep 5, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03G15/01
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In order to shorten cycle up convergence, a stored or resident image is utilized. It is contained on an external control or pixel board forming a part of the machine image output terminal (IOT). The resident image together with a raster output scanner (ROS) is used to form two charge, V.sub.CAD, two discharge, V.sub.DAD and two background, V.sub.Mod patches in every frame for a total of six patches. A pair of electrostatic voltmeters (ESV) are used to read all six patches and control decisions are made on the basis of the average of the two readings for each voltage level. Because of their physical locations relative to the ROS the readings of one ESV are used in forming the two charge area patches while the other ESV is used in forming the discharge area images. Both ESVs are employed for forming the two background patches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.