DRAM Cell with trench capacitor and vertical channel in substrate
US5208657A · kind A · utility
159Cited by
40References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 22, 1991 |
| Grant date | May 4, 1993 |
| Priority date | — |
| Expiry date | Jul 22, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/047
Abstract
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with the capacitor formed in a trench in a substrate and the transistor channel formed by epitaxial growth on the substrate. The transistor source and drain are insulated from the substrate, and the transistor may be adjacent the trench or on the upper portion of the trench sidewalls. Signal charge is stored on the capacitor plate insulated from the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.