Semiconductor memory device having bit lines and word lines different in data reading and data writing
US5208773A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1991 |
| Grant date | May 4, 1993 |
| Priority date | — |
| Expiry date | Mar 13, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is the serial access memory having the improved precharging system of reading bit lines (4). In this serial access memory, an address pointer (9, 114) outputs a signal for selecting one of the reading bit lines (4). Meanwhile, each reading bit line (4) is provided with an MOS transistor (7) for precharging the same. By using the output of the address pointer (9, 114) to control on/off of the MOS transistor (7), the period when each reading bit line (4) is precharged is limited within the period when the reading bit line is selected. As a result, current flowing through the reading bit lines (4) during the data reading can be reduced to achieve the reduction in power consumption of the serial access memory and the increase in the operation speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.