Active selectable digital delay circuit
US5210450A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1992 |
| Grant date | May 11, 1993 |
| Priority date | — |
| Expiry date | Jun 29, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00228
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An active selectable digital delay circuit merges delay elements within a multiplexer to reduce power consumption, area and minimum delay. A current switch forms a basic element of a multiplexer. A group of current switches form an input to the multiplexer and another group of current switches form a control input to the multiplexer, the current switches being in a hierarchical tree configuration. Each input current switch has a resistor between an input voltage and the input to the current switch, the value of the resistor determining the amount of propagation delay between the input and output of the input current switch. With each input having a different resistance value, each input current switch provides a different amount of propagation delay for the input signal so that the delay of the output signal is determined by which input of the multiplexer is selected for output. Multiplexers may be cascaded to extend the selectable delay range between the input and output signals, with each output being input to a plurality of input resistors at the subsequent multiplexer in the cascade.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.