Memory with page mode
US5210723A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 1990 |
| Grant date | May 11, 1993 |
| Priority date | — |
| Expiry date | Oct 31, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory addressable by row and by column and operable in page mode whereby multiple column cycles are performed within a single row cycle, an arrangement is provided for stepping the row address for selected column cycles whereby sustained page mode operation can be provided throughout memory address space. Preferably, stepping occurs in response to a row change signal supplied when a column address strobe becomes active and the direction of stepping is determined by a mode signal supplied when a row address strobe becomes active. Memory segmentation is employed to facilitate simultaneous activation and restoring of multiple rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.