Circuit arrangement for clock regeneration in clock-controlled information processing systems

US5210755A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Werner Nagler · Starnberg, DE
• Lothar Schmidt · Bochum, DE

Key dates

• Filing date: Nov 13, 1990
• Grant date: May 11, 1993
• Expiry date: Nov 13, 2010

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K5/01
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Line terminal groups are redundantly present for reliability reasons. The connecting through of the input lines to the switching matrix network can thereby proceed via different signal paths. In order to avoid disturbances during switch-over between signal paths, the appertaining interfaces are provided with compensation memories. The data contained in the compensation memories are written in or read out in a phase-synchronized and frame-synchronized manner with a uniform clock. The uniform clock is acquired from the electronic switching device base clock of the system. Due to transient time distortions and component tolerances, the base clock must be regenerated with the circuit arrangement of the invention before it is applied to the compensation memories.