Method and apparatus for predicting the effective addresses of future memory load operations in a microprocessor
US5210838A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 15, 1990 |
| Grant date | May 11, 1993 |
| Priority date | — |
| Expiry date | May 15, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for loading a data value for a future LOAD instruction in a microprocessor by predicting the LOAD instruction's effective address. At each occurrence of a LOAD instruction, the effective address used is stored in a memory array which stores a last effective address and a next-to-last effective address. At a specified period before each LOAD instruction, the microprocessor loads a data value from a predicted effective memory address computed from the memory array. The predicted effective memory address is equal to the last effective address plus the difference between the last effective address and the next-to-last effective address. If the predicted effective address equals the actual effective address of the future LOAD instruction, the loaded data value is used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.