Controller for two-way set associative cache
US5210845A · kind A · utility
67Cited by
4References
3Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 28, 1990 |
| Grant date | May 11, 1993 |
| Priority date | — |
| Expiry date | Nov 28, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0884
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache controller (10) which sits in parallel with a microprocessor bus (14, 15, 29) so as not to impede system response in the event of a cache miss. The cache controller tagram (24) is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The external cache memory (8) is organized such that both ways are simultaneously available to a number of available memory modules in the system to thereby allow the way access time to occur in parallel with the tag lookup.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.