Memory address space determination using programmable limit registers with single-ended comparators
US5210850A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 1990 |
| Grant date | May 11, 1993 |
| Priority date | — |
| Expiry date | Jun 15, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for determining cacheable address and write-protect memory address regions in a computer system which includes a programmable single-ended limit register and a single comparator to determine each such region. A programmable limit register associated with each respective memory address region defines a boundary limit for each of the respective memory regions. A single address comparator associated with each respective limit register determines whether a memory address developed by the computer system resides between the respective boundaries provided by the value stored in the respective programmable limit register and a predefined address. The use of a single limit register and a single address comparator for each memory address region reduces the gate count and decreases the input buffer loading in the logic circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.