Clock division chip for computer system which interfaces a slower cache memory controller to be used with a faster processor
US5210858A · kind A · utility
Inventors
Key dates
| Filing date | Oct 17, 1989 |
| Grant date | May 11, 1993 |
| Priority date | — |
| Expiry date | Oct 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clocking control circuit for a computer system and method for receiving a microprocessor clock signal which drives a microprocessor and for supplying a support clock signal having a lower frequency. The support clock frequency drives support interface circuitry such as a peripheral controller, a CPU/memory controller, and a bus bridge interface, and thus causes the support interface circuitry to operate at a lower frequency than the microprocessor. The clocking control circuit ensures synchronization between the support clocking signal and the microprocessor clocking signal. The transmission of control signals between the microprocessor and support interface circuitry is controlled to ensure proper communications between the microprocessor and support circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.