Voltage regulation and latch-up protection circuits

US5212616A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Sang Hoo Dhong · San Jose, US
• Robert L. Franch · Yorktown Heights, US

Key dates

• Filing date: Oct 23, 1991
• Grant date: May 18, 1993
• Expiry date: Oct 23, 2011

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/854

Abstract

An improved latch-up protection circuit is disclosed which prevents damage to a CMOS integrated circuit chip due to transient surges or internal-circuitry initiated latch-ups and which clears any latch-up condition or SCR mode. In each embodiment, the latch-up protection circuit is integrated with an on-chip voltage regulation circuit which provides on-chip power to the internal chip circuitry. A first approach to implementing the latch-up protection circuit is to detect an average current through the power transistor of the voltage regulation circuit over a few microseconds. Should the average current exceed a preset value, then the power transistor is turned off and the power (V.sub.DDI) supplied to the internal chip circuitry is reduced to zero, thereby removing the latch-up condition. In a second approach, the on-chip voltage (V.sub.DDI) supplied to internal chip circuitry is compared with a reference voltage signal representative of the occurrence of a latch-up condition, i.e., with the nominal external power supply. When the on-chip power supply voltage V.sub.DDI becomes lower than the trigger voltage, then the power transistor and voltage regulation circuit is disabled, ther…