Asynchronous time division switching arrangement and a method of operating same
US5212686A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Sep 29, 1989 |
| Grant date | May 18, 1993 |
| Priority date | — |
| Expiry date | Sep 29, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3036
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An asynchronous time division multiplex switching arrangement comprises a serial to parallel converter arranged to receive input packets of data which include routing information, in serial form and convert the packets of data to parallel form. A random access memory is provided in which each packet of data is entered at an addressed location into the memory, and the address is entered in a respective first-in first-out output queue at the tail. The address at the head of the queue is accessed and the packet of data is read from the random access memory into a parallel to serial converter and the packet of data is serially delivered to the associated output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.