Data edge phase sorting circuits
US5212716A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 1991 |
| Grant date | May 18, 1993 |
| Priority date | — |
| Expiry date | Feb 5, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge transitions of a serial data stream relative to a local clock signal. The local clock signal is coupled to a delay line having a plurality of serially connected delay elements, each of which outputs a delay clock of different phase. The sorting circuit includes an extraction circuit coupled to receive the serial data stream for detecting edge transitions in the serial stream and outputting a pulse of predefined duration in response to each detected transition. Coupled to the extraction circuit output is a non-sequential logic circuit, which is also coupled to the local clock through the delay line. The non-sequential logic circuit combines the outputted extraction circuit pulse and the plurality of delay clocks for sorting the pulse relative to the delay clocks. Specific embodiments for the extraction circuit and non-sequential logic circuitry are depicted and described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.