System for single cycle transfer of unmodified data to a next sequentially higher address in a semiconductor memory
US5212780A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 9, 1988 |
| Grant date | May 18, 1993 |
| Priority date | — |
| Expiry date | May 9, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The RAM includes sub-arrays having odd and even memory locations, respectively. A data move instruction results in externally generated row and column address signals which are decoded to cause a first memory location, in one of the sub-arrays, to be selected and data to be read. The next memory location in sequence, in the other of the sub-arrays, is then selected, without necessity for an additional set of row address signals, for writing of the read information. The row decoder includes row indexing circuitry actuatable upon receipt of a shift signal signifying that the first memory location is in the last column of a given row. When the shift signal is received, the write location is automatically selected to be in the succeeding row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.