Method of determining the cause of open-via failures in an integrated circuit
US5214283A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 23, 1991 |
| Grant date | May 25, 1993 |
| Priority date | — |
| Expiry date | Jul 23, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76886
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of analyzing an integrated circuit to determine the cause of an open or resistive intermetal via is disclosed. Instead of conventional cross-sectioning of the suspected via, the method removes the upper of the metal layers at the location of the via, with a selective etch to maintain the presence of the contaminant or other cause of failure at the via. When an isotropic metal etch is used, as is preferred, partial removal of the interlevel dielectric layer will facilitate subsequent analysis by increasing the area to be analyzed. Optical microscopy, SEM microscopy, Auger spectroscopy, EDS spectroscopy, and other conventional analysis techniques may be used at the portion of the circuit within the failed via, to indicate the composition of the undesired contaminant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.