Dynamic memory word line driver scheme
US5214602A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 5, 1991 |
| Grant date | May 25, 1993 |
| Priority date | — |
| Expiry date | Apr 5, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained A DRAM is comprised of bit lines and word lines, memory cells connected to the bit lines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bit line and a high logic level voltage V.sub.dd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high V.sub.pp supply voltage source which is in excess of high logic level voltage V.sub.dd plus one transistor threshold voltage but less than a transistor damaging voltage; means for selecting the word line and means having an input driven by the selecting means for applying the V.…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.