Method for inserting an asynchronous 139,264 kbit/s signal into a 155,520 kbit/s signal
US5214643A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1989 |
| Grant date | May 25, 1993 |
| Priority date | — |
| Expiry date | Apr 17, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5672
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method for inserting an asynchronous 139,264 kbit/s signal into a 155,520 kbit/s signal interlaces an asynchronous 139,264 kbit/s signal from the European digital signal hierarchy into the frame structure of a 155,520 kbit/s signal STM-1 of a network node interface NNI. Bits that are compiled in the form of a virtual container VC-4 in a sub-frame are inserted into the frame structure, which sub-frame is composed of 9 sections each having respectively 261 sub-sections of 1 byte or, respectively, 8 bits each. The first sub-section is reserved for a path overhead (POH). The remaining 260 sub-sections are inventively subdivided into 20 blocks having a first part (W, X, Y, Z) of 1 byte for auxiliary signals and having a second part of 12 bytes composed of information bits (I). This method can be employed at a network node interface NNI in a synchronous digital hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.