Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes
US5214767A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 1989 |
| Grant date | May 25, 1993 |
| Priority date | — |
| Expiry date | Feb 7, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system which includes a direct memory access (DMA) controller which can provide a 32 bit memory address and yet can also provide 24 bit memory address operation to remain compatible with previous systems. The DMA controller also monitors system operation and if only 24 bit address operations are occurring under the control of an external bus master or the DMA controller, the DMA controller drives the top memory address byte provided to a cache memory controller to help insure cache coherency. Additionally, the DMA controller can provide optimal time transfers for word width transfer between an odd starting memory address and an even starting input/output port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.