Method of forming isolation region in semiconductor device
US5215935A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1991 |
| Grant date | Jun 1, 1993 |
| Priority date | — |
| Expiry date | Aug 29, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76202
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a isolation region in a semiconductor device includes the steps of forming an underlying oxide film on a semiconductor substrate, forming a first polysilicon layer on the underlying oxide film, forming a silicon nitride film on the first polysilicon layer, patterning the silicon nitride film such that the silicon nitride film is left only on a circuit element region of the substrate at which a circuit element is to be formed, depositing selectively a second polysilicon layer by vapor deposition on regions of the first polysilicon layer which are exposed by patterning, and forming isolation regions of silicon oxide by thermally oxidizing at least the second and the first polysilicon layers using the patterned nitride film as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.