Buffer circuit having high stability and low quiescent current consumption
US5216291A · kind A · utility
16Cited by
4References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1991 |
| Grant date | Jun 1, 1993 |
| Priority date | — |
| Expiry date | Apr 23, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/462
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A buffer circuit for buffering an applied reference voltage at a low output impedance. The buffer circuit includes an input transistor which is coupled to an external reference voltage and to an external reference current, and a voltage-to-current converter for applying less or more current to an output terminal of the buffer circuit. This provides a substantially temperature-independent and stable buffer circuit which consumes very little quiescent current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.