ECL input buffer for BiCMOS
US5216298A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1992 |
| Grant date | Jun 1, 1993 |
| Priority date | — |
| Expiry date | Jan 10, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An ECL buffer circuit includes an input portion for receiving an input signal at an ECL level, a current switch portion and an output portion. The input portion includes a bipolar transistor (Q1), a level-shift diode (D1) and a constant current source (CS1). The current switch portion includes a first and a second switch circuits and a constant current source (CS2). Each switch circuit includes a resistor (R1, R2) and a bipolar transistor (Q2, Q3). The output portion includes a first and a second output circuits and a constant current source (CS3). Each output circuit includes an emitter follower transistor (Q4, Q5) and a bipolar transistor (Q6, Q7). The first output circuit receives an input signal from the input portion, and the second output circuit receives a reference voltage (V.sub.BB). A by-pass resistor (R3, R4) is connected between the base and the emitter of an emitter follower transistor (Q4, Q5) of each output circuit. When the output signal changes from a second level to a first level, the output signal thereby rapidly changes to a predetermined voltage by the emitter follower transistor (Q4, Q5) at first, then changes to a first level by way of the by-pass operation o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.