Resistorless trim amplifier using MOS devices for feedback elements
US5216385A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 1992 |
| Grant date | Jun 1, 1993 |
| Priority date | — |
| Expiry date | Aug 10, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03G3/001
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A MOS voltage trim amplifier which can multiply an input voltage with a quantized value to generate an output voltage. The MOS trim amplifier comprises a MOS op-amp, a multiplying feedback network, a gate-bias network and startup circuit. The MOS op-amp has a noninverting terminal for receiving the input and an inverting terminal for receiving the feedback network. The multiplying feedback network uses two MOSFETs as feedback elements to provide the voltage ratio for the multiplication. The gate-bias network provides a reference voltage which is a fraction of the input voltage through a MOSFET voltage divider to the feedback MOSFETs. Current mirrors are employed in the gate-bias network to provide a constant stable current through the MOSFET voltage divider to avoid loading the input. The startup circuit generates a bias current to the two feedback MOSFETs to drive them out of their natural off state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.