Digital phase error estimator
US5216554A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 1, 1991 |
| Grant date | Jun 1, 1993 |
| Priority date | — |
| Expiry date | Jul 1, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2007/047
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data clock is synchronized to a modulation coded signal read from a moving storage medium by a phase error estimator circuit that samples the modulation coded signal two times on each side of a detected peak. A first detected data bit taken at a time N- 2 (two time periods prior to the detected peak) is used to predict the expected value of a first modulation coded signal sample taken at a time N- 1 (one time period prior to the detected peak). Similarly, a second detected data bit taken at a time N+ 2 is used to predict the expected value of a second modulation coded signal sample taken at a time N+ 1. Because the first and second detected data bits are able to predict the first and second samples, respectively, the phase error estimator circuit is able to accurately detect phase errors when sampling arbitrary data as would be presented by a (1,k) modulation coded signal. The expected values at times N- 1 and N+ 1 are compared to the actual values and error voltages are determined therefrom. The error voltages are multiplied by the appropriate slope factors, also determined by the first and second detected data bits, and error estimates E(N- 1) and E(N+ 1) are provided. E(N- 1) …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.